Image processor with free flow pipeline bus

ABSTRACT

A digital image processing system has a pipeline bus for transferring addresses and data in parallel among the components of the system, which include an image memory, an address generator and an intensity processor. The pipeline bus includes a pipeline address bus, a pipeline data bus, and a master timing bus. Through the use of handshake signals, the pipeline bus permits a free flow of pipelined data among the components at whatever rate is necessary to complete the particular processing task. Image data is transferred in the form of N×N pixel subimage blocks which can be addressed using a single address.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

The present invention relates to digital image processing systems. Inparticular, the present invention relates to a digital image processingsystem which permits free flow of high speed image data and addresses ina pipelined architecture.

2. Description of the Prior Art.

Over the years many different types of digital image processing systemshave been developed and have found use in various fields such as medicalimaging, remote sensing, and graphic arts. However, this developmentprimarily has been directed toward evolving new processor elements withmore efficient architecture, larger and faster memory elements and moresophisticated input-output elements. There has been little change in thetechnology involved in transferring information among the variouselements in the image processing system.

In digital imaging processing systems, it is typical to use pipelinearchitecture in which parallel digital data flows from one element toanother within the image processor. This pipeline architecture providesthe opportunity for high speed data transfers, since the data istransferred in parallel from one element to the next within the pipelineimage processor. Each element or block within the processor performs adedicated function and passes its results along to the next element inthe processor.

This prior art pipeline image processor architecture, however, hasencountered practical limitations in the computational complexity ofimage processing functions which could be performed. Typically, theprocessor is synchronized to the video monitor, which places a practicallimit on the maximum time a processing task can consume in any one ofthe pipeline processor blocks. That in turn places a limit on thecomputational complexity which can be performed by the image processor.Standard buses such as VME and MULTIBUS are capable of handling imagefunctions of high computational complexity, but are not capable ofsustaining the high transfer rates required of a high performance imageprocessing system.

SUMMARY OF THE INVENTION

The present invention is an image processing system in which the variouscomponents of the image processing system communicate with one anotherby transferring addresses and data in parallel over a pipeline bus.

The image processing system includes image memory means for storingdigital image data, intensity processor means for performing processingfunctions on the image data, and address generator means for generatingaddresses. All of these components communicate with one another over thepipeline bus.

With the present invention, therefore, the pipeline bus uses ahandshaking protocol which permits very high speed address and datatransfer but has a start/stop free flow format which permits thepipeline bus to run at any throughput rate. This is important inpipelined image processing because the computational complexity variesfrom operation to operation. With the present invention, the pipelinebus permits free flow through all components connected to the pipelinebus regardless of the operation being performed, without sacrificingindefinitely sustainable high transfer rates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image processor having a free flowpipeline bus of the present invention.

FIGS. 2A, 2B and 2C show pipeline address (PA) bus, a pipeline data (PD)bus, and a master timing (MT) bus, respectively, of the pipeline bus ofFIG. 1.

FIG. 3 illustrates schematically a 4×4 pixel subimage block used in theimage processor.

FIG. 4 is a diagram illustrating the relationship of system cycles, buscycles and the system clock in a preferred embodiment of the system ofFIG. 1.

FIG. 5 is a diagram showing PA master requests and PA slave responses onthe PA bus of FIG. 2A.

FIG. 6 is a diagram illustrating odd and even system cycles in a systemcycle pair on the PD bus of FIG. 2B.

FIGS. 7A and 7B are diagrams illustrating the arrangement of pixel datatransferred in a 4×4 contiguous block and 2×8 interlaced block transferformats, respectively.

FIG. 8 is a timing diagram showing system cycles and the states ofhandshake lines of the system of FIG. 1.

FIGS. 9A/ and 9B show master bus timing signals of the system, of FIG.1.

FIG. 10 is a functional block diagram of the address generator of thesystem of FIG. 1.

FIG. 11 is a functional block diagram of the pipelined image memory ofthe system of FIG. 1.

FIGS. 11A-11C illustrate the organization and operation of the imagememory where concatenation is required.

FIG. 12 is a functional block diagram of the intensity processor of thesystem of FIG. 1.

FIG. 13 is a functional block diagram of the display formatter of thesystem of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. Digital ImageProcessor 10

FIG. 1 shows digital image processor 10, which is a video rate, freeflow pipelined image processor which uses the pipeline bus architectureof the present invention. In the embodiments shown in FIG. 1, digitalimage processor 10 includes microcomputer controller 12, input interface14, image memory 16, address generator 18, intensity processor 20,display formatter 22, video display 24, and output interface 26.Communication among the components of image processor 10 is providedprimarily over two separate buses: standard bus 28 and pipeline bus 30.Standard bus 28 is preferably an industry standard type of computer bus(such as VME or Multi-bus) and is used for communication of controlinformation between microcomputer controller 14 and the other componentsof digital image processor 10.

The high speed transfer of digital image data, on the other hand, isprovided over pipeline bus 30. As will be described in greater detaillater, pipeline bus 30 includes pipeline address bus (PA) 34, pipelinedata (PD) bus 36, and master timing (MT) bus 38, which are shown inFIGS. 2A-2C, respectively. All transfers of image data among thecomponents of digital image processor 10 are conducted over pipeline bus30.

Microcomputer controller 12 provides an interface between digital imageprocessor 10 and the user. Depending on the particular user commandsprovided to microcomputer controller 12, it sends signals over standardbus 28 to the individual components to configure them to perform thedesired image processing task.

Input interface 14 receives high speed line-by-line input image data, orother input image data, representing a digital image. The input data canbe, for example, from a computer or from data storage devices.

Image memory 16 is a read/write memory which stores digital image data.Input data from input interface 14 is written into image memory 16 (asis processed image data from intensity processor 20). Image data is readfrom image memory 16 to provide input to intensity processor 20 and toprovide output to display formatter 22 and output interface 26.

Address generator 18 generates the stream of addresses ove pipeline bus30 which address image memory 16 to cause digital image data to betransferred; for example, from image memory 16 to intensity processor 20for processing. In addition, address generator 18 communicates directlywith intensity processor 20 over functional address lines 32 to controlthe functional image processing operations being performed by intensityprocessor 20.

Display formatter 22 converts digital image data to display drivesignals which drive video display 24. In one embodiment video display 24is a raster scan video monitor, display formatter 22 converts thedigital image data representing individual pixels of the display intoanalog video signals used by video display 24. Display formatter 22preferably permits asynchronous operation of video display 24 withrespect to the remainder of digital image processor 10. By eliminatingthe need to synchronize operation to the video sync rate of videodisplay 24, a free flow stop/start transfer of data over pipeline bus 30is possible.

Output interface 26 allows digital image processor 10 to communicatewith other digital equipment by a high speed line-by-line transfer ofdata. The format of the data being transmitted by output interface 26is, in one embodiment, similar to the format of data being received byinput interface 14.

Intensity processor 20 performs pipelined image pixel intensitycomputations based on input data received from image memory 16 andfunctional addresses received from address generator 18. In preferredembodiments, intensity processor 20 uses adaptive finite impulseresponse (FIR) filtering to perform a wide variety of differentintensity computations.

To increase the efficiency of data transfer over pipeline bus 30, imagedata is transferred by sub-image blocks. Each block is an N×N square ofspatially contiguous pixels. In the preferred embodiment of the presentinvention which will be discussed, the sub-image block is a 4×4 block --i.e. each block represents sixteen pixels.

Instead of addressing each individual pixel of the image data withinimage memory 16, only a single address (310) is required. In a preferredembodiment of the present invention, this address (310), represents theupper lefthand pixel of each 4×4 pixel block (308), as illustratedschematically in FIG. 3 By addressing sixteen pixels with a singleaddress (308), more efficient transfer of data at higher speed isachieved. In one embodiment of the present invention, up to fouroperations (reading or writing) each are performed at 2.5 megaoperations per second, with each operation representing the addressingof a sixteen-pixel block. This corresponds to a rate of 40 mega pixelsper second/per operation, for a total of 160 mega pixels per second.

In the preferred embodiment which will be described in detail, eachpixel is represented by eight bits. The 4×4 pixel square is transmittedover pipeline bus 30 as four 32-bit sequential words. "Word 0"represents the top row (312) of the 4×4 block and is a 32-bit wordformed by the four 8-bit pixels of the top row. Similarly, "word 1","word 2", and "word 3" are 32-bit words formed by a row of four 8 bitpixels. "Word 3" represents the bottom row of the block.

2. Pipeline Bus 30

Pipeline bus 30 has three major parts, pipeline address (PA) bus 34,pipeline data (PD) bus 36, and the master timing (MT) bus 38. Dependingon the number of components to be connected to pipeline bus 30, and theparticular processing requirements, more than one PA bus 34 and morethan one pipeline data (PD) bus 34 is provided. In the preferredembodiment which will be described, pipeline bus 30 includes two PAbuses 34A and 34B, and six PD buses 36A-36F. PA bus 34 of FIG. 2A and PDbus 36 of FIG. 2B are typical of each PA and PD bus in pipeline bus 30.

PA bus 34 carries physical addresses in image memory 16 of bit-mappeddata, as well as control and routing information for that data. PA bus34 initiates operations that will occur over one or more of the PD buses36. PA bus 34 is a tri-stated bus which is terminated to the high logicstate at its physical start and end points.

A bus cycle on PA bus 34 is the equivalent of two system clocks, asillustrated in FIG. 4. A bus cycle is the duration that a single addressis resident on PA bus 34.

A system cycle (422), as shown in FIG. 4 is a time period that is fourbus cycles (410-413) in duration. The system cycle 422 defines theperiodicy of PA bus 34. Each bus cycle (410-413) of the system cycle(422) is designated as Bus Cycle 0 (410), Bus Cycle 1 (411), Bus Cycle 2(412), or Bus Cycle 3.

The components which use the PA bus 34 are either PA masters or PAslaves. A PA master is the source of data on PA bus 34. A PA slave isthe recipient of data on PA bus 34. All PA slave responses occur twosystem cycles (422) after the system cycle (422) in which the PA masterinitiated the operation.

PA bus 34 is a fixed four-to-one time division multiplexed bus withfixed masters activated each bus cycle (410-413) of system cycle (422).In other words, each PA master has a designated time slot (one of thebus cycles (410-413)) in each system cycle (422).

As shown in FIG. 2A, PA bus 34 has a total of 35 lines, including 26address lines and 9 control lines. "X" physical address lines XP0-XP12(212) and "Y" physical address lines YP0-YPl2 (212) are asserted by thePA master. When the operation involves image memory 16, the input/outputline I/O (212)is set by the PA master to "0". In that case, linesXP0-XP12 (210) define an X physical address in image memory 16(corresponding to the X coordinate of the upper lefthand pixel of thedesired 4×4 subimage block). Similarly, lines YP0-YPl2 (212) define a Yphysical address in image memory 16 corresponding to the Y coordinate ofthe upper left hand pixel of the 4×4 subimage block.

If input/output line I/O (220) is set to "1" by the PA master, theoperation is a parameter passing operation. In that case, lines Xp0-Xp12(210) correspond to bits 0-12 on standard bus 28, and lines YP0-YP10(212) correspond to bits 13-23 of standard bus 28. In that case, YP11and YP12 (of 212) are not used.

The not parallel address ready (NPAR) line (214) is a control orhandshake line which is asserted by the master and is used to indicatethat a valid parallel address is present on PA bus 34. When the NPARline (214) is "0", a valid parallel address is present. When the NPARline (214) is "1", this indicates that PA bus 34 is inactive.

Two system cycles after a pA master has placed a valid parallel addresson PA bus 34, the PA slave to which it is directed is required torespond by asserting the not parallel address detected (NPAD) line (218)and the not parallel address sync (NPAS) line. FIG. 5 showsschematically a PA master's request (510) and a PA slave's response(512) two system cycles later.

When the NPAD line (216) is "0", it indicates that the address has beendetected by a PA slave. When the NPAD line (216) is "1", it indicatesthat an address has not been detected.

The NPAS line (218) permits multiple PA slaves to synchronize to asingle PA master. When the NPAS line (218) is "0"it represents a pAslave request to the PA master to hold the address which had beenasserted on the XP0-XP12 (210) and YP0-YP12 (212) lines. The PA masteris required to repeat that address during its turn in the next systemcycle. When the NPAS line (218) is "1"it indicates that all PA slavesare ready.

The read/write (R/W) line (220) is asserted by the master. A "1" on theR/W line (220) designates a read operation, and a "0" designates a writeoperation.

As discussed previously, the input/output line (I/O) (222) indicateswhether the operation is involving image memory 16 or is a parameterpassing operation. A "0" on the I/O line (222) designates the operationas involving image memory 16, while a "1" designates a parameter passingoperation.

The operation mode (MODE) line (224) is also asserted by the PA master.A "0" on the MODE line(224) designates a non-interlaced transfer, and a"1" indicates an interlace transfer. The I/O (222) and MODE (224) linesare used to select the format for data transferred over PD bus 36. Theoperation of these formats will be described in more detail in thecontext of PD bus 36.

In preferred embodiments of the present invention, image memory 16 iscapable of storing multiple planes of pixel data. The sametwo-dimensional X and Y address coordinates apply to each plane.Multiple planes are used, for example, where three- or four-color imagedata has been scanned and stored. In that case, each plane representsone color. In a three-color application, there are three planes whichcan be simultaneously or individually addressed using the same X and Ycoordinates, simply by altering the PO (226), Pl (228) and PG (230)lines. The plane number lines P0 (226) and P1 (228) define a two bitnumber. The plane group (PG) line (230) selects either single planeoperation (when it is "0") or multiple-plane operation (when it is "1").For multiple-plane operation, the PG line (230) is "1", indicating thatall planes from "0"through the plane number are to be addressed with thesame X and Y address coordinates.

If the PG line (230) is "0", the plane number defined by P0 (216) and P1(228) is simply the plane to be used

for the particular operation. If the PG line (230) is "1", the planenumber designates the final plane of the plane group to be used in thatoperation. The plane number lines P0 (226) and P1 (228) and the PG line(230) are asserted by the PA master.

Pipeline data (PD) bus 36 shown in FIG. 2B contains bit mapped image orgraphics data for transmission between components of image processor 10and preferably is connected to internal parameter registers of eachcomponent for the passing of control parameters. PD bus 36 is atri-stated bus which is terminated at the high state at its physicalstart and end points.

The components which use PD bus 36 can be classifed as PD masters and PDslaves. A PD master is a device that controls transfers on PD bus 36.All PD masters are unconditionally in control of the PD bus during theirtime slot. Each PD master must know a priori the PD slaves which areunconditionally on PD bus 36.

A PD slave is a device that responds to a PD master's request. A PDslave is conditionally on PD bus 36 during a time slot and is activatedby a valid address appearing on PA bus 34. Each PD slave must knowinternally which PD bus to use for every access code on PA bus 34.

As with PA bus 34, the operation of PD bus 36 is defined in terms of buscycles and system cycles (410-413). The bus cycle is the equivalent oftwo system clocks (420), and there are four bus cycles (410-413) in asystem cycle (422). All operations on PD bus 36 take a full system cycle(422) to occur.

All system cycles (422) occur on a pair-wise basis on the PD bus 36.These cycle pairs (616) are broken into odd (612) and even (614) cycle,as illustrated in Fig. 6. A PD master may be in one of four states atany instant. If both the evern (614) and odd (612) cycles areunconditionally off, the PD master is off the PD bus 36. If the evencycle (614) is unconditionally on and the odd cycle (612) isunconditionally off, the PD master uses only the even cycle (614) fordata transfer. Conversely, if the even cycle (614) is unconditionallyoff and odd cycle (612) unconditionally on, the master uses only the oddcycle (612) for data transfer. Finally, if both the even (614) and odd(612) cycles are unconditionally on, the master uses both cycles (612and 614) for data transfer.

As shown in FIG. 2B, PD bus 36 contains 40 lines--thirty-two linethirty-two bits of parallel data. PD00-PD07 (232) define parallel databyte 0. PD10-PDl7 (234) define parallel data byte 1. PD20-PD27 (236)define parallel data byte 2. PD30-PD37 (238) define parallel data byte3.

The source of the data for data bytes 0-3 is (232, 234, 236, 238) isdetermined by the state of the read/write (R/W) line (220) of PA bus 34.If the R/W line (220) is "0", the source of the data bytes is the PDmaster (since this is a write operation). Conversely, if the R/W line(220) is "1" (indicating a read operation), the source of the data byteson PD bus 36 is the PD slave. By using the not write byte linesNWB0-NWB3 (246, 248, 250, 252), either the PD master or the PD slave (inthe case of a write or read operation, respectively) can determinewhether or not particular data bytes are to be used, modifiable on a 4×4block-by-block basis. If one of the not write byte lines (246, 248, 250,252) (for example NWB1 (248)) is a "0", this means that data byte "1" isvalid data. Conversely, if NWB1 line (248) is 1, the source of the datahas indicated that data byte 1 is not to be used during this operation.

The transfer of data over PD bus 36 is in different formats, dependingon the state of the I/O and MODE (224) lines of PA bus 34. If the I/Oline (222) is "1", the thirty-two bits of data appearing on linesPD0-PD7 (232), PD10-PD17 (234), PD20-PD27 (236), and PD30-PD37 (238)remain constant over the entire system cycle (422). This is a parameterpassing operation, and the address appearing on PA bus 34 is derivedfrom standard bus 28.

When the I/O line (222) is "0" meaning that the operation involves imagememory 16, the thirty-two bits of data appearing on PD bus 36 areupdated every bus cycle (410-413) within the system cycle.

The MODE line (224) of PA bus 34 selects whether the thirty-two bitsdata transferred when the I/O line (222) is "0" are in form of a 4×4pixel contiguous region or is in the form of a 2×8pixel interlacedregion. FIG. 7A shows the 4×4subimage block (710) which is passed whenthe MODE, line (224) is "0". This is the standard subimage block (710)used for transferring data over pipeline bus 30. FIG. 7B shows the 2×8interlaced region (712) which is transferred when the MODE line (224) is"1".

The remote data enable (RDE) (254) line of PD bus 36 is used forcommunication with a remote slave through input interface 14. When theRDE line (254) is "0" and the R/W line (220) of PA bus 34 is "0" the PDmaster asserts data over PD bus 36. Conversely, if the RDE line (254) is"1" and the R/W line (220) of PA bus 34 is "1", the PD master receivesdata from the remote slave over PD bus 36.

PD bus 36 includes three handshake lines: the not parallel data ready(NPDR) line (240); the not parallel data accepted (NPDA) line (242); andthe not parallel data sync (NPDS) line (244). The states of these threelines during a typical system cycle is illustrated in FIG. 8.

The NPDR line (240) is asserted by the PD master and indicates whetheror not the PD master is ready to either accept data or to transmit data.A "1" on the NPDR line (240) indicates that the PD master is not ready,while a "0" indicates that the PD master is ready.

If the PD slave has accepted the data or has placed valid data on thedata lines of PD bus 36, it will cause the NPDA line (242), to drop from"1" to "0". A "1" on the NPDA line (242) means that the PD slave has notaccepted data or has not placed data on the data lines. Because the NPDAsignal (242) is a pulse, in the pipelined architecture of the presentinvention there is time to either place new data on the PD bus 36 at thenext Bus cycle (410-413) - or to repeat the same data again. As shown inFIG. the PD master always asserts the NPDR and the PD slave alwaysasserts the NPDA line (242) at the appropriate bus cycle time (e.g. Buscycle 2) (412) to allow the PD master to react to the status.

If any component on PD bus 36 determines that it wants to abort the datatransfer for any reason, it drops the NPDS line during Bus cycle 2(412). Either a PD master or a PD slave can assert the NPDS signal (244). As long as the NPDS line (244) is "1" all components are ready fordata. If the NPDS line (244) is "0", this constitutes a request by theasserting device that the PD master hold the data for this system cycle(422) and repeat it the next valid system cycle (422).

This is particularly important where there are multiple PD slaves on agiven PD bus 36 at one time. If any PD slave feels that it is notprepared for a particular transfer, it can drive the NPDS line (244) low("0") and essentially abort the whole system cycle (422) for allcomponents. Once all of the components agree that they are ready for thetransfer of data, the NPDS line (244) will remain "1" for the entiresystem cycle (422) and the system cycle (422) will proceed normally.This forces a synchronization on PD bus 36 so that all transfers arealways completely valid transfers of data regardless of the number of PDslaves on the PD bus.

As shown in FIG. 2C, master timing (MT) bus 3B includes system clocklines SCKLK+(256) and SCKL-(258) a master sync (MSYNC) line, and asystem initialize (SINIT) line (262). SCLK+(256) and SCKL-(258) arepositive and negative polarities of a differential ECL system clocksignal which, in a preferred embodiment, operates at 20 Mhz. The MSYNCsignal (260) shown in FIG. 9A, dictates the beginning of a timmingcycle.

The SINIT signal (262) shown in FIG. 9B is an initialization signal forthe entire system. Normally, the SINIT signal (262) is "1". When aninitialization is to take place, SINIT (262) is "0" for two systemclocks (420).

3. Address Generator 18

In the embodiment of the present invention shown in FIG. 1, addresscalculation and generation and data calculation are performed separatelyin address generator 18 and intensity processor 20, respectively. Inorder to maintain high throughputs with a pipeline architecture, imageprocessor 10 of the present invention preferably pipelines both addresscalculations as well as data calculations. As a result, the generationof addresses is not a limiting factor in high speed operation.

As described previously, PA bus 34 has a free flow characteristic,meaning that an address placed on PA bus 34 is assigned to a time slotin the pipeline. If that address cannot be immediately accepted by imagememory 16, handshaking takes place which allows the same address toagain be placed on PA bus 34 at the next occurrence of its time slot.This may be repeated as many times as required for the address to beaccepted. This free flow characteristic, therefore, effectively resultsin starting and stopping of PA bus 34.

FIG. 10 shows a preferred embodiment of address generator 18, which is apipelined address generator having a stop/start capability so that it iscompatible with the free flow characteristic of pipeline bus 30.

In the embodiment shown in FIG. 10, address generator 18 includesaddress pipeline 40, first-in, first-out (FIFO) buffer 42, functionaladdress generator 44, and control 46. Address pipeline 40 generatesaddresses at a high rate of speed through a pipelined architecture, andmay be stopped on demand by control 46. Addresses are calculatedparametrically by address pipeline 40 and are supplied to FIFO buffer42, which interfaces with the address lines of PA bus 34. FIFO buffer 42is a first-in, first-out memory that absorbs the speed variationsbetween the starting/stopping of PA bus 34 and the starting/stopping ofaddress pipeline 40. Control 46 interfaces with the handshake lines ofPA bus 34 and provides control signals to address pipeline 40, FIFObuffer 42, and functional address lookup table 44. When the PA bus 34stops and FIFO buffer 42 begins to fill, control 46 halts addresspipeline 40.

Address pipeline 40 includes parameter generator 48, S T U registers 50,world image space calculator 52, X Y Z registers 54, subimage sequencer56, address limiter and address builder 58, and memory management unit(MMU) 60.

The head of the address pipeline is parameter generator 48. This iswhere addressing coordinates S, T and U are calculated by an additiveprocess. In the embodiment of address generator 18 shown in FIG. 10,parametric calculation of addresses is performed directly, rather thanby an accumulative technique used in prior art image processors. Bydirect calculation, each address is calculated separately, withoutreliance on previous addresses. As a result, no accumulated errors areproduced.

Parameter generator 48 passes the S, T and U parameters which it hascalculated to S T U registers 50. World image space calculator 52 drawsthe S T U coordinates from registers 50 and converts them to X Y Zcoordinates (as needed) by use of parametric equations calculated by amultiply and add process. The output of world image space calculator 52is stored in X Y Z registers 54.

The output of X Y Z registers 54 is supplied to subimage sequencer 56,where an M x M block of addresses are constructed around the (X Y Z)base address by a counting process. The X Y Z coordinates are not memorylocations, but rather are logical addresses. Subimage sequencer 56allows the address pipeline 40 to create a subimage which, rather thanbeing a 4×4 block, may be 8×8, l2×12 or 16×16 pixels depending on theparticular operation to be performed.

Address limiter and address builder 58 separate the X Y Z address intorequired and nonrequired bits. The required bits are arranged to build atwo-dimensional or three-dimensional virtual address. The nonrequiredbits are combined to form an overflow detection feature.

MMU 60 is preferably a lookup table where the virtual or logical addressfrom address limiter and address builder 58 is mapped into a physicaladdress space within image memory 16. The output of MMU 60 is a physicaladdress which is supplied to FIFO buffer 42 and ultimately on to PA bus34.

Functional address lookup table 44 also uses the X Y Z coordinates fromregisters 54 to produce a functional address on functional address bus32. This functional address is supplied to intensity processor 20 andare used to select filter coefficients used by intensity processor 20(as will be described in further detail later). The rate at whichfunctional address bus 32 is supplying functional addresses can varyfrom the rate of PA bus 34. In preferred embodiments, however, intensityprocessor 20 has a FIFO buffer for receiving functional addresses, sothat the functional addresses supplied by address generator 18 overfunctional address bus 32 correspond to data being supplied to intensityprocessor 20 over pipeline bus 30.

Address generator 18 shown in FIG. 10, with its parametric pipelineaddress generation, is capable of performing very complex addressgeneration functions without speed degradation. It also allows PA bus 34to operate at whatever speed is required, without any loss of pixel dataor address data or any reduction in the functionality of the addresscalculation functions. This interfacing is achieved throuh FIFO buffer42 and control 46 together with the handshake lines of PA bus 34.

The particular address generation which is performed will, of course,depend upon control commands from microcomputer 12 which are received byaddress generator 18 over standard bus 28. These command load registers(not shown) define coefficients, upper and lower bounds of parameters,and parameter increment values used by address pipeline 40 in thecalculation of coordinates, and ultimately of the addresses which aresupplied over PA bus 34.

4. Image Memory 16

FIG. 11 is a functional block diagram of image memory 16, whichfunctions as a pipelined image memory tile. In the embodiment shown inFIG. 11, image memory 16 includes pipeline address input registers 62Aand 62B, address cache 64, DRAM memory 66, holding register 6B, and dataports 70A-70F. In this embodiment, image memory 16 interfaces throughinput registers 62A and 62B with two PA buses 34A and 34B, respectively.Through output data ports 70A-70F, image memory 16 interfaces with sixPD buses 36A-36F, respectively.

Pipeline address received from address generator 18 over PA buses 34Aand 34B are received by input registers 62A and 62B provided to addresscache 64. In a preferred embodiment, address cache 64 is a first-in,first-out type of memory. When address cache 64 fills so that there aretoo many addresses, it refuses further addresses over PA buses 34A and34B.

All addresses are examined and either ignored, accepted (entered intoaddress cache 64), or rejected with a repeat request using the NPAS lineof PA bus 34A or 34B to indicate a not ready condition.

If a read operation is to be performed (as indicated by the R/W line ofPA bus 34A or 34B), addresses from address cache 64 are read into DRAM66 where they are adjusted for spatial continuity. A sixteen-pixel wordin a 4×4 square configuration of spatially contiguous pixels is loadedinto holding register 68. Once in holding register 68, the 4×4 pixelblock is placed out on one of the six PD buses 36A-36F using the formatdescribed in FIG. 7A.

During a write operation, data representing a 4×4 pixel block is takenfrom one of the data ports 70A-70F and loaded into holding register 68.An address from address cache 64 is then loaded into DRAM array 66 andadjusted for its spatial continuity to select the 4×4 pixel block intowhich the data is to be written.

The free flow characteristics of pipeline bus 30 is reflected in theoperation of image memory 16. If the PD bus 36A-36F has slowed down dueto handshaking, data will not be entering or exiting holding register 68at as high a rate. This slows down the use of addresses from addresscache 64. Since address cache 64 is not using addresses as rapidly, itwill fill and begin rejecting further addresses on PA buses 34A and 34Bso that PA buses 34A and 34B begin to slow down. In other words,handshaking on the PD buses 36A-36F will cause a slow down of memoryfetches in the memory tile which causes a changing effect on PA buses34A and 34B so that there is an interrelationship between the freeflowing characteristics of the PD and PA buses.

An important feature of the images memory (16) is the ability totransmit spatially contiguous data in the 4×4 pixel format for anyaddress received over the PA bus (defined by XPA0-XPA12 (210) andYPA0-YPA12) (212). Conventional buses permit only addresses that areinteger multiples of the block size (or word size) of the bus. Forexample a thirty-two bit, four-pixel READ or WRITE on a conventional buswould permit only integer multiples of four to be received over theaddress bus. This can lead to severe performance degradation in someimage processing functions because multiple READs would be required toform a region of computational dependency. In large data base systems,such as those typical of high resolution image processing, this mustalso be valid even when the image spans multiple memory cards. Sincethere is a spatial boundary between memory cards, multiple memory cardsmay be required to contribute a single 4×4 block transfer as shown.

In image memory 16 of the present invention a pixel at X, Y comes fromthe memory group M, N defined by: ##EQU1## A memory tile has its memorychips organized into the sixteen memory groups (5/8,5/8) through (3,3)shown in FIG. 11. A memory tile has a size defined by the number ofmemory chips and the size of the memory chip (i.e., 32 256K DRAMScreates a 1024×1024 memory title (1110). Each group (M,N) holds all ofthe pixels in the memory tile that are defined by Eq. 1 above, providedthat X and Y are not greater than the size of the tile. These separatepixels are held within different locations (L) (1112) within the memorygroup as shown in FIG. 11A.

Spatially contiguous 4×4 subimage blocks are read/written from thememory tile by controlling the locations within each group. A single 4×4subimage block (1120) may draw from as many as four different locations,(1122, 1124, 1126, 1128) within groups as shown in FIG. 11B.

When memory regions larger than a single memory tile are required,multiple memory cards (1130, 1132, 1134, 1136) can be abutted to createan effectively larger memory title (1138). This larger memory tile(1138) must be transparent to all cards (1130-1136) on the pipeline bus.An example is the creation of a 2048×2048 memory region (1138), fromfour 1024-1024 tiles, (1130-1136), as shown in FIG. 11C.

If a memory request requires a border region that overlaps multiplememory tiles, each memory title must contribute certain pixels to the4×4 block (1140) as if the request was from the center of a tile. Thisprocess is the concatenation of memory tiles.

In general for a single 4×4 block (1140) up to four memory tiles (asillustrated in Figure 11C) may required to contribute to a singlesubimage block (1140) transfer, depending on the location of the blockwith respect to the boundaries of the memory tiles (1130-1136).

This is implemented as follows. Each memory tile (TILE 5/8) (1130)decodes the PA address of itself and the three neighbors (TILES 1-3)(1132-1136) adjacent to it. It declares one of five states to exist: (1)not one of TILE 5/8(1130), TILE 1 (1132), TILE 2 (1134), TILE 3(1136)(2) TILE 5/8(1130) addressed; (3) TILE 1 (1132) addressed, (4) TILE 2(1134) addressed, (5) TILE 3 (1136) addressed. If condition (1) isdeclared this memory tile does not participate in the operation. If oneof conditions (2)-(5) exists memory tile must decide if it will berequired to contribute to the corresponding PD bus transfer. This isaccomplished by examining the lower address to see if it falls within athree-pixel border along the memory tile seams (boundaries).

If the address falls outside the three-pixel border, then noconcatenation will occur. If it falls within the three-pixel borderconcatenation must occur. If concatenation must occur, the two leastsignificant bits (LSB) of X, and the two least significant bits (LSB) ofY and the quadrant are stored internally in the memory tile and used tocontrol the data when transmitted over the PD bus. The PD bus iscontrolled as follows:

If concatenation must occur, image memory 16 decodes the quadrant, the XLSBs, the Y LSBs and the bus cycle (0, 1, 2, 3) on the PD bus toidentify which bus cycles and bytes the memory tile must be 0N(contributing to the transfer) or OFF (letting another memory tilecontribute to this transfer). This circuit causes the PD bus memoryconcatenation in such a way the receiving master device perceives nodifference on the PD bus. The NPDS line is dropped if image memory 16 isnot ready to contribute its data.

5. Intensity Processor 20

FIG. 12 is a functional block diagram of intensity processor 20. In thisembodiment, intensity processor 20 is a circuit that performs pipelinedimage pixel intensity computations using adaptive finite impulseresponse (FIR) filtering. By changing filter coefficents, a wide varietyof different intensity computation operations can be performed.

In the embodiment shown in FIG. 12, intensity processor 20 has fourinput ports (functional address input port 72, I2 port 74, I1 port 76,and TAG port 78) and one output port B0. Image processor 20 includes 12buffer 82, I1 buffer 84, TAG buffer 86, control RAM 88, I2 functionalmemory and coefficient store 90, I1 functional memory 92, subimagescanner 94, adaptive FIR 96, accumulator 98, output functional memory100, and output buffer 102.

The I1 (1210), I2 (1212) and TAG (1214) inputs are bit-mapped imagesreceived from image memory 16. All three inputs can be generatedsimultaneously with the same address from address generator 18 to imagememory 16, or may be generated separately and transmitted over three ofthe four address channels on the PA bus without sacrificing throughput.In other words, I1 (1210), I2 (1212) and TAG (1214) represent differentplanes which can be addressed. The input images I1 (1210), I2 (1212) andTAG (1214) are received over three separate PD buses 36A-36C in subimageblocks with a 4×4 pixel square geometry. These subimage blocks areconcatenated together to form larger subimages and then are fed into anarithmetic pipeline.

The functional address input is received over functional address bus 32from address generator 18 and shares I2 buffer 82 with I2 port 74. Thefunctional addresses select filter coefficients to be used by adaptiveFIR filter 96. Filter coefficients that change with time are loaded intoI2 functional memory and coefficient store 90 (which is implemented in apreferred embodiment as a look-up table) and are selected by thefunctional address (which is different depending on the address in theimage).

The TAG image (1214) is fed into control RAM 88 that selectscoefficients (tap weights) to be applied to the I1 (1210) and I2 (1212)images. In other words, the TAG input (1214) allows the intensityprocessing operation to vary on a pixel-by-pixel basis. The selection ofcoefficients by the functional addresses can also be affected by the TAGinputs (1214) through control codes supplied by control RAM 88 to store90.

I1 function memory 92 and I2 function memory and coefficient store 90are preferabl look-up tables which perform preprocessing of the I1(1210) and I2(1212) images received from buffers 84 and 82,respectively. The particular function memory page of the look-up tableused for preprocessing is based on control codes from control RAM 88,which are selected by the TAG inputs (1214). A typical form ofpreprocessing performed in FM 90 and FM 92 is gray scale transformation.

The subimage scanner 94 reads pixels in the region of computationaldependency and inserts them into the pipeline through control RAM 88 ina sequential fashion. This allows variation of filter size weights basedon computational dependency of surrounding pixels.

The arithmetic pipelines for I1 and I2 merge at adaptive FIR filter 96where arithmetic and logical operations are performed and the resultsaccumulated in accumulator 98. In the block diagram, FIR 96 includes acombiner for performing what may be termed "post filtering" combinerfunctions such as add, subtract, multiply, divide, OR, XOR and AND.These combiner functions are selected by combiner codes from control RAM88 based on the TAG inputs. The final results are passed to outputfunctional memory 100 and are stored in output buffer 102. Output buffer102 acts as a first-in/first-out memory and permits pipelined intensitycomputations to occur. Upper buffer 102 is connected, through upper port80, to pipeline data buses 36A-36F.

By using adaptive FIR filtering, function memories for preprocessing,and an arithmetic and logical combiner for postfiltering functions,intensity processor 20 is capable of performing a wide variety ofdifferent intensity processing computations which are selectable byaddress generator 18 under the control of microcomputer controller 12and by the TAG inputs (1214). All that is required to change from onetype of image processing to another is simply to change the coefficientsor tap weights to the adaptive FIR filter, function memory pages, and/orcombiner codes. These tap weights, function memory and combiner codescan be changed through the functional addresses produced by addressgenerator 18, and also are varied by the TAG input.

6. Display Formatter 22

FIG. 13 shows a preferred embodiment of display formatter 22, whichconverts pipelined image data which is encoded in a square 4×4 pixelformat from pipeline bus 30 to asynchronous serial (line-by-line) videosignals supplied to video display 24. Display formatter 22 decouples theoutput timing supplied to video display 24 from the input or systemtiming of pipeline bus 30. As a result, pipeline bus 30 can operate on astop/start free flow basis without interfering with operation of videodisplay 24.

As shown in FIG. 13, display formatter 22 includes a pair of doublebuffered address converter RAMS 104A and 104B. Subimage block pixel datais received from pipeline bus 30 by buffers 106A and 106B which areassociated with RAMs 104A and 104B, respectively. The outputs of RAMs104A and 104B are supplied to buffers 108A and 108B, respectively. Theoutputs of buffers 108A and 108B are provided to D/A converter 110, andthe output is an analog video signal which is supplied to video display24.

The control circuitry for display formatter 22 includes write selectcircuit 112, and address select circuits 114A and 114B.

Buffers 106A and 106B are operated using the system clock (420) providedby pipeline bus 30. One of the RAMs 104A or 104B is being written intousing system timing produced by the system clock (420), while the otherRAM is being read out using the timing (video clock) (116) of videodisplay 24. The RAMs are reversed after a given length of time (forexample four video lines) sufficient to allow both input and outputcompletion.

For example, during a time when RAM 104A is being written into, thewrite A signal (1306) is being supplied to RAM A (104) and the addressis being supplied from address select 114A to RAM 104A at a ratedetermined by the system clock (420). The starting address is the inputaddress (1310) supplied to address select circuit 114A, and subsequentaddresses are provided at the system clock (420) rate.

At the same time, RAM 104B is being read out by addresses from addressselect circuit 114B. The starting address (1312) is supplied by theoutput address input to address select circuit 114B, and the addressessupplied to RAM 104B are changed at the video clock rate.

As data is being read from RAM 104B into buffer 10BB, the previouslyread out data from RAM 104A which is in buffer 108A is being supplied toD/A converter 110 at the video clock (116) rate

Display formatter 22 provides a number of significant advantages. First,by decoupling output timing from input timing, small time variationsbetween pipeline bus 30 and video display 24 are permitted withouthaving an adverse effect on one another. For example, variations invideo timing as required for GENLOCK video capability is permittedwithout affecting system timing of the pipeline bus 30.

Second, dislay format 22 allows pipeline bus 30 to stop and startindependently of video burst requirements as long as the average datarate is maintained over the swapping time of RAMs 104A and 104B. Thispermits utilization of horizontal blanking time for writing.

Third, display formatter 22 provides a conversion from subimage blockpixel configurations (which are highly efficient for transferring imagedata on pipeline bus 30 to a data format which is compatible with normaloperation of video display 24 (such as a line-by-line raster scanformat).

7. Conclusion

The image processor of the present invention provides a highlyefficient, adaptable, and high speed image processing architecture. Thepipeline bus 30 of the present invention permits free flow datatransfers so that a wide range of image processing functions of varyingcomputational complexity can be performed.

The subimage block configuration used to transfer image data overpipeline bus 30 offers significantly increased speed and efficientaddressing since only a single address needs to be provided in order toobtain an entire block of pixel data.

The parametric, pipelined, direct calculation of addresses in addressgenerator 18 also offers high speed and accuracy. The use of adaptiveFIR filtering for all intensity processing operations lends itselfideally to a high speed and highly flexible system. Finally, theasynchronous operation of display formatter 22 allows a free flowpipeline bus architecture while providing video display capability.

Although the present invention has been described with reference topreferred embodiments, workers skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention.

What is claimed is:
 1. A digital image processing systemcomprising:pipeline bus means for transmitting addresses and data, andfor transmitting handshake signals for controlling flow of addresses anddata over the pipeline bus means; image memory means connected to thepipeline bus means for storing digital image data; address generatormeans connected to the pipeline bus means for generating the addresses;and processor means connected to the pipeline bus means for performingprocessing operations on the digital image data received over thepipeline bus means.
 2. The digital image processing system of claim 1wherein the pipeline bus means comprises:pipeline address (PA) bus meansover which the addresses are transmitted; and pipeline data (PD) busmeans over which the data is transmitted.
 3. The digital imageprocessing system of claim 2 wherein the pipeline data bus meanstransmits handshake signals for indicating data is ready, for indicatingdata is accepted, and for requesting that data be held and repeated. 4.The digital image processing system of claim 2 wherein the pipelineaddress bus means transmits handshake signals for requesting that anaddress be held and repeated.
 5. The digital image processing system ofclaim 2 wherein the pipeline bus means further includes:master timingbus means for distributing clock and synchronization signals whichdefine bus cycles and system cycles, each system cycle being formed by aplurality of bus cycles.
 6. The digital image processing system of claim5 wherein the PA bus means is time-division multiplexed.
 7. The digitalimage processing system of claim 5 wherein an address is resident on thePA bus means for one bus cycle.
 8. The digital image processing systemof claim 5 wherein a data transfer operation over the PD bus meansrequires a system cycle to complete.
 9. The digital image processingsystem of claim 2 wherein the pipeline bus means transmits digital imagedata in a format which represents a multipixel subimage block.
 10. Thedigital image processing system of claim 9 wherein the subimage block isa rectangular block of pixels.
 11. The digital image processing systemof claim wherein the pixels of the subimage block are contiguous. 12.The digital image processing system of claim wherein the subimage blockis an N×N block of contiguous pixels.
 13. The digital image processingsystem of claim wherein N=4.
 14. The digital image processing system ofclaim 11 wherein the address represents a location of one of the pixelsof the subimage block.
 15. The digital image processing system of claim9 wherein the pixel whose location is represented by the address islocated in a corner of the subimage block.
 16. The digital imageprocessing system of claim 14 wherein the address generator meanscomprises:address generation pipeline means for producing a sequence ofaddresses; and first in/first out (FIFO) buffer means for 1 receivingthe sequence of addresses from the address generation pipeline means andproviding the addresses to the pipeline bus means.
 17. The digital imageprocessing system of claim 16 and further comprising:control meansconnected to the address generation pipeline means and to first in/firstout (FIFO) buffer means and responsive to the handshake signals, thecontrol means for stopping and starting the address generation pipelinemeans.
 18. The digital image prcocessing system of claim 16 wherein theaddress generation pipeline means comprises:means for parametricallycalculating virtual addresses; and means for converting the virtualaddresses to physical addresses and providing the physical addresses tothe FIFO buffer means.
 19. The digital image processing system of claimwherein the means for parametrically calculating comprises:parametergenerator means for generating a set of parameter values for eachaddress; and world image space calculator means for calculating virtualaddress coordinates as a function cf the set of parameter values. 20.The digital image processing system of claim 19 wherein the addressgeneration pipeline means further comprises:means for constructing ablock of addresses around a base address defined by the virtual addresscoordinates; and means for separating the block of addresses intorequired and nonrequired bits to produce the virtual address.
 21. Thedigital image processing system of claim 20 wherein the means forconverting includes a lookup table for mapping the virtual address ontophysical address space to produce the physical address.
 22. The digitalimage processing system of claim 18 wherein the means for parametricallycalculating performs a direct address calculation for each new addressto be generated.
 23. The digital image processing system of claim 10wherein the processor means includes:adaptive finite impulse response(FIR) filter means for performing arithmetic and logical operations onthe digital image data as a function of filter coefficients; and meansfor providing the filter coefficients to the adaptive FIR filter means.24. The digital image processing system of claim wherein the addressgenerator means produces functional addresses associated with theaddresses transmitted over the pipeline bus, and wherein the means forproviding the filter coefficients selects the filter coefficients as afunction of the functional addresses.
 25. The digital image processingsystem of claim 23 wherein the image memory means stores, as part of theimage data, a TAG field of bit-mapped data, and wherein the means forproviding filter coefficients is responsive to the TAG field ofbit-mapped data.
 26. The digital image processing system of claim 1 andfurther comprising:video display means for displaying images based uponthe video signals; and display formatter means connected to the pipelinebus means for converting data from the pipeline bus means to the videosignals.
 27. The digital image processing system of claim 26 wherein thedisplay formatter means allows the video display means and the pipelinebus means to operate asynchronously.
 28. The digital image processingsystem of claim 27 wherein the display formatter means includes:firstand second address converter means; and control means responsive to asystem clock from the pipeline bus means and a video clock from thevideo display means, the control means during a first portion of eachoperating cycle of the display formatter writing digital image data fromthe pipeline bus means into the first address converter means at a ratecontrolled by the system clock while reading digital image data from thesecond address converter means at a rate controlled by the video clockto produce the video signals, and during a second portion of eachoperating cycle reading digital image data from the first addressconverter means at a rate controlled by the video clock to produce thevideo signals while writing digital image data from the pipeline busmeans into the second address converter means at a rate controlled bythe system clock.
 29. A digital image processing system comprising:imagememory means for storing digital image data for a plurality of pixels;address generator means for addressing the image memory means byproviding an address representing a predetermined pixel of a multipixelsubimage block; processor means for receiving and processing pixel datafor the subimage block; and pipeline bus means connected to the imagememory means, the address means and the processor means for transmittingthe addresses produced by the address generator means and datarepresenting subimage blocks.
 30. The digital image processing system ofclaim 29 wherein the subimage block is a rectangular block of pixels.31. The digital image processing system of claim 30 wherein the pixelsof the subimage block are contiguous.
 32. The digital image processingsystem of claim 31 wherein the subimage block is an N×N block ofcontiguous pixels.
 33. The digital image processing system of claim 32wherein N=4.
 34. The digital image processing system of claim 30 whereinthe address provided by the address generator means represents a cornerpixel of the subimage block.
 35. A pipeline intensity processor for usein a digital image processing system, the intensity processorcomprising:input means for receiving digital image data to be processed;adaptive finite impulse response (FIR) filter means, coupled to theinput means, for performing arithmetic and logical operations on thedigital image data as a function of filter coefficients; and means,coupled to the filter means, for varying the filter coefficients. 36.The pipeline intensity processor of claim 35 wherein the means forvarying the filter coefficients selects filter coefficients as afunction of functional addresses which are associated with physicaladdresses of the digital image data.
 37. The pipeline intensityprocessor of claim 35 wherein the digital image data includes a TAGimage, and wherein the means for varying the filter coefficients selectsfilter coefficients as a function of the TAG image.
 38. A pipeline busfor transferring addresses and data in parallel among a plurality ofcomponents of a digital image processing system, the pipeline buscomprising:a pipeline address bus connected within the digital imageprocessing system over which a physical address is transmitted; apipeline data bus connected within the digital image processing systemover which data is transmitted, the pipeline data bus includinghandshake lines by which a master indicates it has data ready and bywhich a slave indicates whether it has accepted the data and whether themaster is requested to hold and repeat the data; and a master timing busconnected within the digital image processing system for distributingclock and synchronization signals which define bus cycles and systemcycles, each of the system cycles being defined by N bus cycles.
 39. Adigital image processing system comprising:pipeline bus means connectedwithin the digital image processing system for transmitting addressesand digital image data; address generation pipeline means connectedwithin the digital image processing system for producing a sequence ofaddresses; first in/first out (FIFO) buffer means connected within thedigital image processing system for receiving the sequence of addressesfrom the address generation pipeline means and providing the addressesto the pipeline bus means; image memory means connected to the pipelinebus means and addressable by the addresses for storing the digital imagedata; and processor means connected to the pipeline bus means forperforming processing operations on the digital image data received overthe pipeline bus means.
 40. The digital image processing system of claim39 wherein the pipeline bus means includes means for transmittinghandshake signals for controlling flow of addresses and digital imagedata over the pipeline means, and further comprising:control meansresponsive to the handshake signals for stopping and starting theaddress generation pipeline means.
 41. The digital image processingsystem of claim 39 wherein the address generation pipeline meanscomprises:means for parametrically calculating virtual addresses; andmeans for converting the virtual addresses to physical addresses andproviding the physical addresses to the FIFO buffer means.
 42. Thedigital image processing system of claim 41 wherein the means forparametrically calculating comprises:parameter generator means forgenerating a set of parameter values for each address; and world imagespace calculator means for calculating virtual address coordinates as afunction of the set of parameter values.
 43. The digital imageprocessing system of claim 42 wherein the address generation pipelinemeans further comprises:means for constructing a block of addressesaround a base address defined by the virtual address coordinates; andmeans for separating the block of addresses into required andnonrequired bits to produce the virtual address.
 44. The digital imageprocessing system of claim 43 wherein the means for converting includesa lookup table for mapping the virtual address onto physical addressspace to produce the physical address.
 45. The digital image processingsystem of claim 41 wherein the means for parametrically calculatingperforms a direct address calculation for each new address to begenerated.
 46. A digital image processing system comprising:pipeline busmeans for transmitting addresses and data; image memory means connectedto the pipeline bus means for storing digital image data; addressgenerator means connected to the pipeline bus means for generating theaddresses; processor means connected to the pipeline bus means forperforming processing operations on the digital image data received overthe pipeline bus means; video display means for displaying images basedupon the video signals; and display formatter means connected to thepipeline bus means for asynchronously converting data from the pipelinebus means to the video signals.
 47. The digital image processing systemof claim 46 wherein the display formatter means includes:first andsecond address converter means; and control means responsive to a systemclock from the pipeline bus means and a video clock from the videodisplay means, the control means during a first portion of eachoperating cycle of the display formatter writing digital image data fromthe pipeline bus means into the first address converter means at a ratecontrolled by the system clock while reading digital image data from thesecond address converter means at a rate controlled by the video clockto produce the video signals, and during a second portion of eachoperating cycle reading digital image data from the first addressconverter means at a rate controlled by the video clock to produce thevideo signals while writing digital image data from the pipeline busmeans into the second address converter means at a rate controlled bythe system clock.